1. Field of the Invention
The present invention relates generally to multi-phase clock generator circuits and more particularly to a novel delay locked loop (DLL) circuit providing a multi-phase clock using a same amount of delay stages in DLL but producing smaller clock spacing resolution than the propogation delay of delay stages in DLL.
2. Description of the Prior Art
Multi-phase clock is generated through delay locked loop (DLL). Spacing or resolution between these clocks are limited to the propagation delay of each stage in DLL.
FIG. 1 is a prior art DLL circuit 10 showing the current method of generating a Phase Shifted clock using a DLL. In this circuit 10, comprising a N stage DLL, e.g., N=32, the phase shift is equal to Tck/N where the Tck is the “locked” clock cycle and N is the number of stages. That is:
Tpd=Tck/N, where Tpd is limited to the propagation delay of each stage.
It would be highly desirable to provide a circuit apparatus and method of providing a phase shifted clock at sub-picosecond granularity wherein the time difference between rising clock edge appearance between each delay stage is Tpd/M, where M is equal to the number of clock cycles captured within the DLL and Tpd is the propagation delay of each delay stage.
It would be highly desirable to provide a DLL circuit apparatus and method for capturing M clock cycles where M is an odd number (greater than one) of clock cycles (e.g., 3 or 5 clocks) in the DLL.
It would be highly desirable to provide a DLL circuit apparatus and method for capturing M number of clock cycles, the number of clock cycles is a prime number greater than 1 that would provide a multi-phase clock resolution in an N-stage DLL that is less than the propagation delay of a single stage.